The present invention relates to current-mirror-type sense-amplifier circuits that can be effectively applied in a multivalued-information memory for storing three or more values in each of its memory cells.
There has been proposed a multivalued-information memory capable of storing three or more values in each of its memory cells. This is realized in such a manner that plural threshold potential values are preset for each memory cell by changing an amount of impurities induced into channel areas of the memory cell for a mask ROM or by changing an amount of accumulating charge of floating gates for a flash E.sup.2 PROM. The discrimination of these threshold potentials is conducted by comparing each potential at each bit line with plural reference values corresponding to the threshold potential values of the memory cell.
In case of storing, e.g., four-value information in each memory cell with bit-line potentials corresponding to respective threshold potential values expressed as VTH1, VTH2, VTH3 and VTH4, the first reference potential value VREF1 is set at a certain value between the values VTH1 and VTH2, the second reference potential value VREF2 is set at a certain value between the values VTH2 and VTH3 and the third reference potential value VREF3 is set at a certain value between the values VTH3 and VTH4. The above reference values are used by sub sense-amplifiers SN1, SN2 and SN3 as shown in FIG. 1. A bit-line potential VBIT is one of the values VTH1, VTH2, VTH3 and VTH4 and, therefore, output signals SA1, SA2 and SA3 corresponding to the bit-line potentials are obtained. FIG. 2 shows a relationship between bit-line potentials and reference potentials. CE is a signal for activating a sense amplifier. Two bit-information (D1, D2 in FIG. 4) according to the above-described output signals SA1, SA2 and SA3 can be readout by a circuit of FIG. 3.
Japanese Laid-open Patent Publication No. 5-217385 discloses a sense amplifier circuit used for a mask ROM. In the disclosure, as shown in FIG. 5, the sense amplifier is applied for a mask ROM for storing four-valued information in each of memory cells, wherein four bit-line potentials VTH1, VTH2, VTH3 and VTH4 are used as reference potentials corresponding to respective thresholds of the memory cell. The amplifier circuit is provided with three sub sense-amplifiers SL1, SL2 and SL3 each of which consists of a current mirror circuit. The first sub sense-amplifier SL1 is given the first and second bit-line potentials VTH1 and VTH2 as reference potentials, the second sub sense-amplifier SL2 is given the second and third bit-line potentials VTH2 and VTH3 as reference potentials and the third sub sense-amplifier SL3 is given the third and fourth bit-line potentials VTH3 and VTH4. This enables the amplifier circuit to use reference bit-lines having the same construction as that of the corresponding bit-lines of the memory cell, thus realizing stable reading of the potentials.
Referring now to FIGS. 6 and 7, a current-mirror-type sense-amplifier will be described as below:
As seen in FIG. 6, the first static inverter is composed of a n-type metal-oxide silicon field-effect transistor MOSFET QN1 and a p-type MOSFET QP1 and the second static inverter is composed of a n-type MOSFET QN2 and a p-type MOSFET QP2: both the inverters are in parallel to each other and connected each at one end to a ground potential (GND) through a n-type MOSFET QN3. The static inverters are also connected each at the other end to a power-source potential (Vcc). With the signal CE for activating the sense-amplifier, the n-type MOSFET QN3 conducts bringing the sense-amplifier into the state being ready to work. The p-type MOSFET QP1 and QP2 compose a load side of the current mirror. The n-type MOSFET QN1 and QN2 are supplied with input potentials to be compared with each other. Namely, a reference potential VREF is input to a gate of the n-type MOSFET QN1 and a bit-line potential VBIT is fed to a gate of the n-type MOSFET QN2. A difference between those potentials is detected and output as an output signal VOUT.
In the first static inverter, the p-type MOSFET QP1 operating in the saturated mode (region) possesses a load characteristic curve (a1) and the n-type MOSFET QN1 possesses a drive characteristic curve (b1) as shown in FIG. 7. These curves (a1) and (b1) intersect at a point V1=A1. On the other hand, the p-type MOSFET QP2 of the second static inverter has a gate voltage V1 equal to that of the p-type MOSFET QP1 of the first inverter and has, therefore, a load characteristic curve (c1). With VREF=VBIT, the drive characteristic curve of the n-type MOSFET QN2 of the second static inverter becomes equal to b1. Both the characteristic curves intersect at a point of VOUT=A1. The drive characteristic of the n-type MOSFET QN2 of the second static inverter, since the curves b1 and c1 intersect in a saturated region, changes to the curves d1 and e1 with a small change in the bit-line potential. Therefore, the intersection of the curve b1 with the load characteristic curve c1 considerably shifts from the VOUT=B1 to a point of VOUT=C1. Thus, a small voltage signal can be sensed and amplified faster at high sensitivity as the characteristic I of FIG. 7.
Referring to FIG. 1, the operation of the amplifier circuit used in a multivalued memory will be described below.
In an initial state of the sense-amplifier circuit, bit-lines (VBIT) and reference-lines (VREF) are usually pre-charged to set at an initial potential V0 (FIG. 2) before reading-out operation. When a memory cell is then discharged, the bit-line potential (VBIT) reaches one of the bit-line potentials (VTH1, VTH2, VTH3, VTH4) depending on the threshold of the memory cell. On the other hand, the reference line potential takes an intermediate potential value (VREF1, VREF2, VREF3) of the respective bit-lines. For example, when a bit-line potential VBIT is equal to VTH2 according to the threshold of the memory cell to be read-out, VBIT at the sub sense-amplifier SN1 becomes higher than VREF1, VBIT at the sub sense-amplifier SN2 becomes lower than VREF2 and VBIT at the sub sense-amplifier SN3 becomes lower than VREF3. At this time, the sub sense-amplifiers SN1, SN2 and SN3 have output signals SA1=0, SA2=1 and SA3=1 respectively and an output information (D1, D2)=(0, 1) is obtained through a circuit shown in FIG. 3. Similarly, an output information as shown in FIG. 4 can be obtained when bit-line potentials are of VTH1, VTH3 and VTH4.
In the current-mirror-type sense-amplifier, the transition of its output SA becomes slower with a smaller difference between a bit-line potential and a reference potential. Accordingly, each sub sense-amplifier having a small difference (.DELTA.V=.vertline.VBIT-VREF.vertline.) between a bit-line potential and a reference potential may have a considerable delay time of transition, by which the delay time of the sense amplifier circuit is defined. Consequently, the sense amplifier circuit of FIG. 1 causes the memory to have an access time that is defined by SN1 with a least difference value (.DELTA.V) at the bit-line potential being equal to VTH1, by SN1 or SN2 at VTH2, by SN2 or SN3 at VTH3 and by SN3 at VTH4.
The sense-amplifier circuit used for a multivalued information memory is composed of a plurality of sub sense-amplifiers corresponding to respective reference potentials. If the sub sense-amplifiers are the same in construction, they have different sensitivity (gain) depending on the input potential signals irrespective of the same difference (.DELTA.V). The gain characteristics of the sub sense-amplifiers are shown in FIG. 10.
In other words, the sense amplifier circuit may have an operating characteristic II shown in FIG. 8 at a higher reference potential, in which load and drive characteristic curves intersect at a point A2 outside the saturated region of the drive characteristic. Therefore, a change in bit-line potential VBIT causes the second static inverter to change the drive characteristic of its MOSFET QN2 into curves d2 and e2, resulting in that the intersection between the drive characteristic e2 and the load characteristic c2 is shifted from the point VOUT=B2 to the point VOUT=C2. Thus, the same change in the bit-line potential may cause .vertline.B2-C2.vertline.&lt;.vertline.B1-C1.vertline. to reduce the gain (sensitivity) of the amplifier circuit. At the same time, a drain current increases because of the condition Id2&gt;Id1.
On the other hand, the sense amplifier circuit may have an operating characteristic III (FIG. 9) at the lower reference potential, in which the load and drive characteristic curves intersect at a point A3 outside the saturated region of the drive characteristic. Therefore, a change in bit-line potential VBIT causes .vertline.B3-C3.vertline.&lt;.vertline.B1-C1.vertline. and reduces the gain (sensitivity) of the amplifier circuit. In this case, a drain current is reduced because of Id3&lt;Id1, resulting in increasing the delay time of the sub sense-amplifiers. Furthermore, n-type MOSFET cannot conduct while the reference potential is lower than its threshold potential (Vtn). This makes it impossible to obtain a correct output of the sense amplifier circuit.
To reduce the access time to the multivalued information memory, respective sub sense-amplifiers must operate according to the operating characteristic I or the like as shown in FIG. 7. This can be realized by decreasing the difference between the reference potentials of the sub sense-amplifiers. However, a small difference between the reference potentials makes it impossible to provide a large difference between the reference potential and the bit-line potential for each sub sense-amplifier. This results in an unwanted decrease in the sensitivity of the sense amplifier circuit.
The sense amplifier circuit for the multivalued information memory, which is composed of plural sub-sense-amplifiers, requires different periods for obtaining comparison results by the sub sense-amplifiers and, therefore, has a final operation rate determined by the latest time at which output of the latest sub sense-amplifier can be obtained. The latest sub-amplifier has the operating characteristic III shown in FIG. 9.
The present invention was made to solve the above-described problems of the conventional sense amplifiers.
In a memory constructed as shown in FIG. 11, potentials VBIT of bit-lines BL of the memory increase as corresponding threshold values for memory cells MC increase. In the sense amplifier circuit of FIG. 1, the reference potentials VREF1, VREF2 and VREF3 correspond to the memory cells having threshold values in the ascending order. The sub sense-amplifiers SN1, SN2 and SN3 have operating characteristics III, I and II respectively (FIG. 10). These sub-sense-amplifiers are called as n-type polarity sub sense-amplifiers (n-type sense amplifiers).
The sense-amplifier circuit constructed as shown in FIG. 12, in which all n-type MOSFETs are provided with reversed conducting channels, has the reference potentials VREF1, VREF2 and VREF3 corresponding to the memory cells having threshold values in the ascending order. In this case, the sub sense-amplifiers SP1, SP2 and SP3 have operating characteristics II, I and III respectively (see FIG. 10) just contrary to the n-type sense amplifiers. These sub sense-amplifiers are called as p-type polarity sub sense-amplifiers (p-type sense amplifiers).
Accordingly, a sub-sense-amplifier of the p-type polarity is used as a sub sense-amplifier corresponding to the reference potential VREF1 and a n-type (polarity) sub-sense-amplifier of the n-type polarity is used as a sub-sense-amplifier corresponding to the reference potential VREF3 to avoid the operating characteristic III. A sub-sense-amplifier corresponding to the reference potential VREF2 may be of any polarity (p- or n-polarity). Thus, all sub sense-amplifiers have either of the characteristics I and II realizing the reduction of the access time.
Accordingly, the present invention is directed to a sense-amplifier circuit comprising sub sense-amplifiers being different in polarity depending on reference potentials, which circuit is used as a sense-amplifier circuit including plural mirror-current-type sub-sense-amplifiers corresponding to plural reference potentials.
The present invention is also directed to a sense-amplifier circuit comprising plural current-mirror-type sub-sense-amplifiers, wherein the sub sense-amplifier having the highest reference potential is of the n-type polarity and the sub sense-amplifier having the lowest reference potential is of the p-type polarity.
The limitation of the operating current enables the sub-sense-amplifier having the operating characteristic II to operate at the same level of current and voltage as the sub-sense-amplifier having the operating characteristic I. In an n-type sense-amplifier shown in FIG. 6, a gate potential of a MOSFET QN3 is preset at a specified intermediate potential being lower than a sum of its source/drain voltage (Vsd) and threshold voltage (Vth) so that the MOSFET QN3 can operate in a saturated region in which it serves as a constant current source. The optimization of the intermediate potential can equalize the current value of the QN3 to that of the characteristic I and, thereby, can attain the equivalent sensitivity. Namely, the n-type sense-amplifier MOSFET QN3 can be given the operating characteristic IV similar to the characteristic I by providing it with current limiting means as shown in FIG. 13.
Referring now to FIG. 13, the operation of the sense amplifier having the operating characteristic IV will be described below in detail.
It is assumed that an n-type MOSFET QN3 composing a switching element has a drain potential Vs determined as a point at balance between VREF and VBIT by a specified control input Vx (i.e., a gate potential of the n-type MOSFET QN3). When the source/gate voltage Vsg of the n-type MOSFET QN1 and QN2 drops by Vs the sub sense-amplifiers have the operating characteristic IV shown in FIG. 13, which curve intersects with the curve a22 at a point V1=VOUT=A22 in the balanced state (VBIT=VEREF). This improves the sensitivity of the sense amplifier so that the output VOUT against a change in the bit-line potential from B2-C2 of FIG. 14 (the same as shown in FIG. 8) to B22-C22 of FIG. 13. The power consumption of the sense amplifier can be reduced from Id2 to Id1. The control input VX is desirable to meet the condition (source/gate voltage Vsg-threshold voltage Vth)&lt;(source/drain voltage Vsd) allowing the n-type MOSFET QN3 to operate in the saturated region in which it serves as a stabilized current source. The above description on the n-type sense amplifier is also applied to the p-type sense amplifier.
The present invention as described above is directed to a sense-amplifier circuit that can faster read data from a multivalued information memory by means of adaptively designing the polarity and current values of respective sub-sense-amplifiers composing the sense-amplifier circuit.